Abstract.

The paper considers the response surface construction of analog circuit. Each surface point is represented by circuit performances and can be obtained by simulating the circuit with corresponding parameters (simulation point). Surface and simulation points loaded in the Data Base (DB) can provide effective tools for analog design. However, high computational efforts of the simulation require effective sampling algorithm that is presented in the paper. The algorithm is based on minimizing the number of simulation points under the given requirements for response surface error tolerance. The error is estimated as the difference between linear and quadratic approximations of the surface in the intermediate points of the coordinate axes. The error of the vector performance is defined as maximal error of its components. The next simulation point is taken as the candidate point with maximal error estimate. In multidimensional case the next point is choose between candidate points in all coordinate axes, and other points of parameter space are generated by obtained uneven rectangular grid. Numerical example presented in the paper (high-speed operational amplifier) demonstrated the improvement of simulation points distribution due to the proposed algorithm in the comparison with the distribution obtained by the uniform grid.

Keywords:

computer-aided design, analog circuit, approximation, Data Base, optimization, circuit simulation, response surface, surrogate model

PP. 3-13.

References

1. Toumazou, C., Makris, C.A. Analog IC design automation. I. Automated circuit generation: new concepts and methods // IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995. 14(2), pp. 218–238.
2. Degrauwe, M.G.R., et al. IDAC: an interactive design tool for analog CMOS circuits // IEEE J. Solid-State Circuits, 1987. 22(6), pp. 1106–1116.
3. Hershenson, M.D.M., Boyd, S.P., Lee, T.H.: GPCAD: a tool for CMOS op-amp synthesis // IEEE/ACM Int. Conf. on Computer-Aided Design, 1998.
4. Kuo-Hsuan, M.: Po-Cheng, P., Hung-Ming, C. Integrated hierarchical synthesis of analog/RF circuits with accurate performance mapping // International Symposium on Quality Electronic Design, Santa Clara, 2011.
5. Nye W., Riley D.C., Sangiovanni-Vincentelli A. et al., DELIGHT.SPICE: an optimization-based system for the design of integrated circuits // IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1988. 7(4), pp. 501–519.
6. Krasnicki M., Phelps R., Rutenbar R.A. et al., MAELSTROM: efficient simulation-based synthesis for custom analog cells, in Design Automation Conference, 1999. pp. 945–950
7. Massier T., Graeb H., Schlichtmann U., The sizing rules method for CMOS and bipolar analog integrated circuit synthesis // IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008. 27(12), pp. 2209–2222.
8. Koziel, Slawomir, Leifsson, Leifur (Eds.), Surrogate-Based Modeling and Optimization: Applications in Engineering, Springer Science & Business Media, Springer New York Heidelberg Dordrecht London, 2013. P. 412
9. Garitselov O., Mohanty S.P., Kougianos E., A Comparative Study of Metamodels for Fast and Accurate Simulation of Nano-CMOS Circuits // IEEE Transactions on Semiconductor Manufacturing, 2012, V. 25, no. 1
10. Burnaev E.V., Zaytsev A.A., Surrogatnoe modelirovanie raznotochnyh dannyh v sluchae vyborok bol'shogo razmera [Surrogate modeling of mutlifidelity data for large samples], Informacionnye processy, 2015 V. 15, no. 1, pp. 97–100
11. Date C. J., Darwen H. «A Guide to the SQL standard: a user`s guide to the standard database language SQL»// 4th ed., Addison Wesley, USA 1997, ISBN 978-0-201-96426-4
12. MySQL 5.6 Reference Manual // https://dev.mysql.com/doc/refman/5.6/en/ (accessed November 2,17)
13. Johnston T, Alsulmi M. Cicotti P. Taufer M., Performance Tuning of MapReduce Jobs Using Surrogate-Based Modeling // Procedia Computer Science Vol. 51, 2015, Pages 49–59. ICCS 2015 International Conference оn Computational Science
14. KK Vu, C D'Ambrosio, Y Hamadi, L Liberti, Surrogate-based methods for black-box optimization // International Transactions in Operational Research, 2017, 24 (3), pp. 393-424